The market demands a low-power, high accuracy analog-to-digital converter (ADC). Therefore, it is desirable to reduce a size of a CMOS comparator in the ADC to a submicron scale because smaller comparators have less input capacitance and thus the stage that drives the comparators requires less power. However, as gate size of the transistors in the comparator become smaller, a reduction in gate size increases the intrinsic offset voltage in a differential comparator. The offset voltage is not a function that is designed into a circuit, but is an inherent characteristic of submicron scale devices. Compounding this problem is randomness of an offset voltage magnitude. Therefore, when an analog signal is compared by a submicron-size comparator, the analog signal is compared to the sum of the offset voltage and the ideal reference voltage. Comparator accuracy is reduced when the analog signal is compared to both the reference voltage and the offset voltage instead of only to the reference voltage. Changes in comparator accuracy affect ADC accuracy. Thus, ADC accuracy decreases with a reduction in comparator size. This is due to the fact that the standard deviation of the offset voltage increases as the transistor gate size is decreased.
What is needed is an ADC with a small, low-power comparator that does not reduce ADC accuracy. Also needed is an apparatus and method to counter the effects of the offset voltage by calibrating the ADC as well as overcome other shortcomings noted above.